1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, those which use an SOI (silicon on insulator) substrate.
Priority is claimed on Japanese Patent Application No. 2007-139105, filed May 25, 2007, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In an SOI substrate which is widely used in semiconductor devices, an (embedded) insulating film is provided on a silicon substrate, and a silicon layer is further provided thereon.
A semiconductor memory device using the above-described SOI and having an FBC (floating body cell) memory cell has been developed, in which a part corresponding to the channel area of a MOS transistor (as a floating-body transistor) formed in a silicon layer on an embedded insulating film is formed as a floating body where a charge as data is stored.
In a DRAM (dynamic random access memory) cell which uses such a floating-body transistor as an access transistor, when a time period in which the bit-line (electric) potential of each non-selected cell is H (high) is long, a charge is stored in the relevant floating-body area, and the potential thereof increases.
After that, at the instant when the level of the bit-line potential shifts to L (low), a leakage current flows due to a parasitic bipolar action, by which the charge as the data (i.e., data charge) stored in the relevant capacitor is lost, and an erroneous operation such as a data loss occurs. Such a phenomenon may be found in Non-Patent Documents 1, 2, and 3.
Generally, in most DRAMs, each bit line is pre-charged at an intermediate potential between H and L. In this case, if the above-described floating body is applied to the access transistor of a DRAM cell, and a bit line, which has not been accessed for a relatively long time, is accessed, then at the instant when the bit line shifts from the intermediate potential to the L-level potential, a data charge stored in another non-selected memory cell connected to the present bit line is lost.
In addition, the potential of the floating body increases due to the charge stored in the relevant floating body area, so that the threshold voltage of the access transistor is decreased.
In accordance with such a decrease in the threshold voltage, the subthreshold leakage current of the access transistor increases, so that the data charge stored in the relevant non-selected memory cell is lost.
In order to solve such a problem of the data-charge loss, a DRAM having a body refresh mode for discharging a charge stored in the body of a MOS transistor is known (see, for example, Patent Document 1).    Patent Document 1: Japanese Unexamined Patent Application, First Publication No. H09-246483.    Non-Patent Document 1: “Measurement of Transient Effects in SO1 DRAM/SRAM Access Transistors”, IEEE ELECTRON DEVICE LETTERS, Vol. 17, No. 5, May 1996, pp 193-195    Non-Patent Document 2: “Low-Voltage Transient Bipolar Effect Induced by Dynamic Floating-Body Charging in Scaled PD/SOI MOSFET's”, IEEE ELECTRON DEVICE LETTERS, Vol. 17, No. 5, May 1996, pp 196-198    Non-Patent Document 3: “Fully depleted surrounding gate transistor (SGT) for 70 nm DRAM and beyond”, IEDM '02, Digest of Technical Papers, 2002, pp 275-278
However, in Patent Document 1, as the body refresh mode is added to the normal operation mode, the operation becomes complex, which thereby increases both the circuit size and the chip area.
In addition, as a dedicated power supply for performing the body refresh is necessary, the chip area is further increased going against an important requirement for the reduction of the chip size.
Furthermore, as the body refresh is necessary in addition to the normal refresh operation, the busy rate with respect to the access prohibition to a DRAM cell increases, which affects the access time, and also causes deviation from the standard specification, thereby removing compatibility with other DRAMs.
The above problem is overcome by making the precharge potential of the relevant bit line be “L”, so that no charge is stored in the floating body area.
However, in a period in which the page mode access is performed, a bit line selected within a few ten to a few hundred microseconds may maintain the H-level potential.
In this case, it is impossible to solve a problem in which at the instant when the period of the page mode access is completed and the relevant bit line is precharged to the “L” potential, a data charge stored in a non-selected memory cell, which has been connected to the precharged bit line, is lost.